As it is well known, power MOS devices, especially low voltage ones, have been characterised, especially during the last years, by a continuous increase of the integration density of transistor elementary structures, following a process of dimension reduction, so called “scaling down” typical of integration techniques so called “Very Large-Scale Integration” (VLSI).
In transistor elementary structures, this has implied the use of thinner and thinner gate oxides, shallower and shallower junctions, and shallower and shallower channel lengths. Power MOS devices formed by completely submicrometric transistor elementary structures are, nowadays, a reality present on the market.
This technological development proceeds from the application need of having smaller and smaller output resistances from transistor elementary structures and higher and higher switching speeds.
The need is even more important when driving power MOS devices, with lower and lower gate voltages, so as to allow the corresponding driving circuits [driver] a low voltage output (1.8-2.5 Volt).
From the technological viewpoint the previously exposed necessities result in the need of suitably designing the transistor elementary structure, whose repetition will constitute the power MOS device. In particular, the gate dielectric thickness, typically silicon oxide, is more and more reduced so as to obtain threshold voltage values lower than a volt without deteriorating the breakdown characteristics of the MOS device due to a possible punch through effect of the channel whose length is more and more reduced.
However, this implies drawbacks. For example, in terms of switching speed, the reduction of the gate dielectric thickness, together with the higher integration density, implies an increase of the MOS device capacitances and thus a slowdown in the switching speed. Moreover, the switching speed does not exclusively depend on the capacitance but also on the resistance seen from the driver for loading and unloading the capacitive elements of the power MOS device. Such resistance takes the name of inner gate resistance and it depends on the physical and geometrical characteristics of the group of all the elementary structures.
In particular, FIG. 1 schematically shows an equivalent electric circuit of 1 of n elementary MOS transistors Ti (i=1 . . . n) in parallel, which constitute a power MOS device. Such elementary transistors have a common control terminal Gate and common conduction terminals Drain and Source. This circuit also shows a gate biasing network wherein the resistive contribution brought by inner resistances Ri (i=1 . . . n) of the n elementary MOS transistors Ti constituting the power MOS device is highlighted.
All in all, for improving the dynamic performances of a power MOS device, as the one shown for example in FIG. 1, it is necessary to reduce to the minimum not only the total gate capacitance but also the resistance thereof, determined by the contribution of the resistances Ri, so as to reduce the time constant (RC), given by the product between the total gate resistance by the device capacitance.
So far the known technique has been oriented on technological and circuit innovation paths to separately solve the problems correlated to the minimization of the gate capacitance and resistance of a power MOS device.
A first known solution, turned towards minimizing the capacitance, consists in integrating, in MOS technologies, gate dielectrics different from thermal SiO2 such as for example, hafnium oxide, aluminium oxide, multilayers of silicon oxide/silicon nitride, etc.
However, the activities linked to the adoption of alternative materials are long and subject to tests which could require prohibitive times for the current market of the devices at issue, making a solution to the highlighted problem not attainable.
A second known solution, turned towards minimizing the capacitance, by increasing the switching speed of the device, provides a change of the geometry of the single transistor elementary structure of the power MOS device. In particular, this structure is changed in the gate dielectric in active area, which is realized with two layers having different thickness:                a first relatively thin layer is realized on the source channel, so as to make a driving of the low threshold voltage MOS device possible;        another layer of greater thickness is realized so that it is extended to the sole region of the gate/drain capacitor (intercell), so as to remarkably reduce the transition capacitance of the MOS device.        
A technique for realizing power VDMOS devices with vertical diffusion, both with channel n, and with channel p, and with double gate oxide thickness in active area, is described in the U.S. Pat. Nos. 6,222,232 and 6,326,271 and the resulting structure is shown in FIG. 2, globally indicated with 2 and wherein source, body and drain regions are respectively indicated with 13, 12 and 11.
In this technique, the definition procedure of the gate electrode mainly requires a thermal growth of a silicon oxide thick film OX, its photolithographic definition in active area regions, the successive growth of a thin gate oxide film OXG which will surmount a channel ch. The deposition of a gate poly electrode (doped polysilicon or polysilicon stack/metallic silicide) and the definition of the gate geometries through suitable phototechnique maskings then follow.
The rest of the process is that typical of a vertical diffusion power MOS, with realization of a channel through lateral diffusion of a well (of the p type in a channel n device and of the n type in the device of opposite polarity), and of a small heavily doped source well, opening through phototechnique of source and gate contacts, and front and rear metallization of the so called “semiconductor slice”, which substantially represents the substrate whereon the MOS is integrated.
Unfortunately, the prior art for the realization of a gate with double oxide thickness, of a transistor elementary structure of power MOS devices, clashes on the growing need of increasing the integration density however safeguarding the alignment of the planar structures in active area. In fact, the prior art provides the use of a photolithography to define the thick oxide region OX in the transistor elementary structure and of a successive and more delicate photolithography step for the definition of the gate poly electrode geometry.
The need of having a symmetrical and uniform diffused channel imposes, in this case, a great margin between the delimitation of the gate electrode, whose projection is indicated with A in FIG. 2, and the edge of the structure in central thick oxide OX, whose projection is indicated with B in FIG. 2.
A margin indicated with L in FIG. 2 must be sufficiently wide as to ensure that possible maximum misalignments in the lithographic definition of the gate poly electrode do not determine a channel extension Lch under the thick oxide OX however in an asymmetrical way.
Obviously, the presence of this margin reduces the integration density of the device on semiconductor.
In the prior art there exist “self-aligning” methods able to reduce the above margin L and based on the formation of spacers realized at the edges of the thick oxide, as well highlighted in FIG. 3, wherein source, body and drain regions will be indicated as in FIG. 2. FIG. 3 shows a structure 3 with double self-aligning gate thickness of power VDMOS devices. This structure has two VDMOS devices, indicated with T1 and T2, having a first gate dielectric thickness, indicated respectively with OXG1 and OXG2 and a second gate dielectric thickness, indicated respectively with OX1 and OX2.
Opposite spacers SP delimit an opening IN, through which the plants for the formation of body wells are realized, from the start of the thick oxide OX1 and OX2. A margin L′, comprised between the projection B′ of an end of the opening IN through which the plants for the formation of body wells are realized and the projection A′ of the end of the thick oxide OX1 nearer to the opening IN, is lower than the margin D1 shown in FIG. 2.
Unfortunately, also these self-aligning methods of the known type have serious drawbacks; being based on anisotropic etchings, they tie the margin L′ between the openings through which the plants for the formation of body wells are realized and the start of the thick oxide, to the thickness of the polysilicon or dielectric layers used for their realization.
The thickness of these layers being normally lower than the micrometer it follows that also this margin L′, and, in particular, the channel length L′ch, will be lower than the micrometer. If on one side this represents an advantage for the submicrometric structures used in low voltage applications, this fact represents a limit for the technologies destined to high voltage applications since channel lengths L′ch lower than the micrometer can trigger premature breakdown problems.
Other techniques being known in the literature, for example as described in the U.S. Pat. No. 5,933,734, are orientated on technological and circuit innovation paths, to solve the problems correlated with the minimization of the gate resistance of a power MOS device. The structure is realized with the technique described in the cited patent is shown in FIG. 4, wherein source, body and drain regions will be indicated as in FIGS. 2 and 3, also overlapped onto a substrate 10. Therein, a gate mesh comprising gate electrodes EGi (i=1 . . . n) is realized with a suitably doped polysilicon pls layer placed in parallel to a metal or metallic silicide sic, at a lower resistivity with respect to the polysilicon.
The technical problem is that of defining a process for realizing a high integration density power MOS device, with a gate electrode having double oxide thickness, having such structural characteristics as to be used also in technologies with scale dimensions VLSI, but with channel dimensions being not necessarily submicrometric, overcoming the limits and/or the drawbacks of the prior art.